2026

Journal articles

  • C. Shi, T. Yang, R. Shioya, H. Yamaki, H. Honda, and S. Miwa, A Comprehensive Analysis of the Impact of Sub 10-nm CNFET Technology on 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units, Integration, the VLSI Journal, Vol.106, No.102583, 16 pages, Elsevier (2026).

Conference/workshop

  • K. Yoshida, H. Yamaki, H. Honda, K. Sato, and S. Miwa, Combining System- and User-Level Approaches to Improving Energy Efficiency in GPU-Based Supercomputers, The International Conference on High Performance Computing in Asia-Pacific Region (HPCASIA'26) Workshops (to appear)
  • Y. Li, C. Shi, S. Miwa, and K. Sano, Rethinking the Bit Length of Post-Training Quantization for LLM Accuracy and Hardware Efficiency, The International Conference on High Performance Computing in Asia-Pacific Region (HPCASIA'26) (poster presentation) (to appear)
  • C. Shi, B. Adhi, L. Teng, J. Liu, S. Miwa, and K. Sano, Towards Unified Acceleration: Weight-Stationary GEMM on HPC-oriented Elastic CGRAs, The International Conference on High Performance Computing in Asia-Pacific Region (HPCASIA'26) (to appear)

2025

Journal articles

  • K. Yoshida, R. Sakamoto, K. Sato, A. Bhatele, H. Yamaki, H. Honda, and S. Miwa, VAHRM: Variation-Aware Resource Management in Heterogeneous Supercomputing Systems, IEEE Transactions on Parallel and Distributed Systems, Vol. 36, Issue 8, pp.1713-1727 (2025).
  • S. Sato, S. Miwa, H. Honda, and H. Yamaki, Feedback-based Dynamic Traffic Balancing for Multipath Routing in ISP Networks, IEICE Transactions on Information and Systems (accepted)

Conference/workshop

  • S. Miwa, E. Sekikawa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors, The 30th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1350-1356 (2025) (acceptance rate: 168/587=29%).
  • C. Shi, T. Koizumi, R. Shioya, H. Yamaki, H. Honda, and S. Miwa, MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations, 2025 62nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation) (2025)
  • C. Shi, B. Adhi, Lin Teng, S. Miwa, and K. Sano, Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI, 2025 62nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation) (2025)
  • R. Tanaka, H. Yamaki, S. Miwa, and H. Honda, Analysis of MPI Parallel Code Generated by GPT-4o, ISC High Performance 2025 International Workshops, 14 pages (2025) (Best Paper Award).
  • K. Shimojima, H. Yamaki, H. Honda, S. Matsuo, A. Takefusa, and S. Miwa, MPI-SGX: Enabling Confidential Computing for MPI Parallel Applications with Intel SGX Technology, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC25, poster presentation) (2025) (Best Poster Candidate)

2024

Journal articles

  • C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CNFET-OCL: Open-source Cell Libraries for Advanced CNFET Technologies, IEEE Access, Vol.12, pp. 165335-165347 (2024).
  • K. Yoshida, S. Miwa, H. Yamaki, and H. Honda, Analyzing the Impact of CUDA Versions on GPU Applications, Parallel Computing, Vol.120, No.103081, 10 pages, Elsevier (2024).

Conference/workshop

  • K. Shimojima, S. Miwa, H. Yamaki, and H. Honda, Evaluating MPI Performance on SGX and Gramine, 2024 IEEE International Conference on Cluster Computing Workshops (CLUSTER Workshops) (poster presentation), pp. 172-173 (Sep 2024)
  • C. Shi, B. Adhi, S. Miwa, and K. Sano, Post-Route Power Estimation: a Case Study of RIKEN-CGRA, 2024 IEEE International Conference on Cluster Computing Workshops (CLUSTER Workshops) (poster presentation), pp. 166-167 (Sep 2024)
  • T. Kusaba, Y. Awaki, K. Yoshida, S. Miwa, H. Yamaki, T. Hanawa, and H. Honda, Power-Efficiency Variation on A64FX Supercomputers and its Application to System Operation, 2024 IEEE International Conference on Cluster Computing Workshops (CLUSTER Workshops), pp. 55-65 (Sep 2024).
  • C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, Analysis of 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units Designed with 7-nm CNFET, 2024 61st ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation) (Jun 2024).

Invited conference/seminar talks

  • S. Miwa, Design Challenges of CNFET Processors, ARCHIDE: Workshop on Architecture Design Methodologies and Ecosystems for HPC and Scientific Edge Computing, Lawrence Berkeley National Laboratory, Berkeley, CA, USA (Aug 2024)

2023

Conference/workshop

  • S. Miwa, and S. Matsuo, Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors, The SC'23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis (SC-W'23), pp. 1850-1858 (Nov 2023).
  • C. Shi, S. Miwa, T. Yang, R. Shioya, H. Yamaki, and H. Honda, CNFET7: An Open Source Cell Library for 7-nm CNFET Technology, The 28th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.763-768 (acceptance rate: 102/328=31%).

2022

Conference/workshop

  • K. Yoshida, R. Sageyama, S. Miwa, H. Yamaki, and H. Honda, Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs, The 51st International Conference on Parallel Processing (ICPP), No. 65, pp.1-12 (acceptance rate: 84/311=27%).

2021

Journal articles

  • S. Miwa, I. Laguna, and M. Schulz, PredCom: A Predictive Approach to Collecting Communication Traces, IEEE Transactions on Parallel and Distributed Systems, Vol. 32, Issue 1, pp.45-58 (2021).

2020

Journal articles

  • K. Tanaka, H. Yamaki, S. Miwa, H. Honda, Evaluating Architecture-Level Optimization in Packet Processing Caches, Computer Networks, Vol.181, No.107550, 10 pages, Elsevier (2020).
  • H. Yamaki, H. Nishi, S. Miwa, H. Honda, RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache, IEICE TRANSACTIONS on Information and Systems, Vol.E103-D, No.12, pp.2590-2599 (2020).
  • S. Miwa, M. Ishihara, H. Yamaki, H. Honda, and M. Schulz, Footprint-Based DIMM Hotplug, Footprint-Based DIMM Hotplug, IEEE Transactions on Computers, Vol. 69, Issue 2, pp.172-184 (2020) (Featured Paper in the February 2020 issue).

2019

Conference/workshop

  • G. Georgakoudis, N. Jain, T. Ono, K. Inoue, S. Miwa, and A. Bhatele, Evaluating the Impact of Energy Efficient Networks on HPC Workloads, 26th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) (to appear) (acceptance rate: 39/173=23%).
  • Y. Inouchi, H. Yamaki, S. Miwa, and T. Tsumura, Functionally-Predefined Kernel: a Way to Reduce CNN Computation, The 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim 2019), 6 pages (Aug 2019) (Best paper award for computers track: 1/27=3.7%).
  • K. Tanaka, H. Yamaki, S. Miwa, and H. Honda, Multi-Level Packet Processing Caches, The 2019 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), 3 pages (Apr 2019).

Invited conference/seminar talks

  • S. Miwa, Variation of GPU Power in Supercomputing Systems, George Washington University, Washington, DC, USA (Sep 2019).

2018

Conference/workshop

  • K. Tanaka, H. Yamaki, S. Miwa, and H. Honda, Optimizing Memory Hierarchy within an Internet Router for High-Throughput and Energy-Efficient Packet Processing, ACM Student Research Competition (in conjunction with the 51st Annual ACM/IEEE International Symposium on Microarchitecture) (poster presentation) (Oct 2018).
  • H. Yamaki, H. Nishi, S. Miwa, and H. Honda, Data Prediction for Response Flows in Packet Processing Cache, 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC), No.110 (Jun 2018).
  • I. Miyoshi, S. Miwa, K. Inoue, and M. Kondo, Run-Time DFS/DCT Optimization for Power-Constrained HPC Systems, The International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2018) (poster presentation) (Jan 2018).

Invited conference/seminar talks

  • T. Ono, Y. Kakibuka, N. Jain, A. Bhatele, S. Miwa, and K. Inoue, Extending A Network Simulator for Power/Performance Prediction of Large Scale Interconnection Networks, Modeling and Simulation of HPC Architectures and Applications (the SIAM PP18 mini-symposium) (Mar 2018).

Books

  • M. Kondo, I. Miyoshi, K. Inoue, and S. Miwa, Power Management Framework for Post-Petascale Supercomputers, Book Chapter in Advanced Software Technologies for Post-Peta Scale Computing—The Japanese Post-Peta CREST Research Project— edited by M. Sato, pp.249–269, Springer (Dec 2018).

2017

Domestic non-refereed symposiums

  • The six technical reports were published.

Invited conference/seminar talks

  • The two seminar talks were done.

2016

Journal articles

  • Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, and H. Nakamura, A Runtime Optimization Selection Framework to Realize Energy Efficient Network-on-Chip, IEICE TRANSACTIONS on Information and Systems, Vol.E99-D, No.5, pp.2881-2890 (2016).

Conference/workshop

  • M. Ohba, S. Miwa, S. Shindo, T. Tsumura, H. Yamaki, and H. Honda, Initial Study of Reconfigurable Neural Network Accelerators, The 7th International Workshop on Advances in Networking and Computing (poster presentation), pp.707-709, (Nov 2016).
  • S. Shindo, M. Ohba, T. Tsumura, and S. Miwa, Evaluation of Task Mapping on Multicore Neural Network Accelerators, The 4th International Workshop on Computer Systems and Architectures, pp.415-421, (Nov 2016).

Domestic non-refereed symposium

  • The five technical reports were published.

Invited conference talks

  • S. Miwa, Low-power computers with increased hardware, IPSJ-ONE in the 78th National Convention of IPSJ, (Mar 2016).

2015

Conference/workshop

  • S. Miwa, and H. Nakamura, Profile-based Power Shifting in Interconnection Networks with On/Off Links, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15), pp.37:1-37:11 (Nov 2015).
  • S. Miwa, and H. Honda, Memory Hotplug for Energy Savings of HPC systems, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15, poster) (Nov 2015).
  • E. Arima, H. Noguchi, T. Nakada, S. Miwa, S. Takeda, S. Fujita, and H. Nakamura, Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches, The 33rd IEEE International Conference on Computer Design (ICCD'15), pp.157-164 (Oct 2015).
  • Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, and H. Nakamura, Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections, The 33rd IEEE International Conference on Computer Design (ICCD'15) (poster presentation), pp.484-487 (Oct 2015).
  • E. Arima, S. Miwa, T. Nakada, S. Takeda, H. Noguchi, S. Fujita, and H. Nakamura, Subarray Level Power-Gating in STT-MRAM Caches to Mitigate Energy Impact of Peripheral Circuits, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation), (June 2015).

Invited conference talks

  • S. Takeda, H. Noguchi, K. Nomura, S. Fujita, S. Miwa, E. Arima, T. Nakada, and H. Nakamura, Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors, The 12th International SoC Design Conference, pp.153-154 (Nov 2015).

Domestic seminar

  • Y. Ishikawa, A. Koshiba, R. Sakamoto, Y. Wada, S. Miwa, M. Kondo, M. Namiki, H. Honda: Initial Study for Operand-Aware Power Gating on Execution Units, IPSJ-SIGARC-209 (in Japanese), No.14, pp.1-2, 2015 (to appear).

Book review

  • S. Miwa: Biblio Talk "THINK LIKE ZUCK", IPSJ Magagine (in Japanese), Vol.56, No.5, pp.500-501 (2015).

Before 2014

Miwa lab started since Mar 2015. You can see the past publications by Assoc. Prof. Miwa in his personal web site.