2019

Conference/workshop proceedings

  • Y. Inouchi, H. Yamaki, S. Miwa, and T. Tsumura, Functionally-Predefined Kernel: a Way to Reduce CNN Computation, The 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim 2019), 6 pages (Aug 2019) (Best paper award for computers track: 1/27=3.7%).
  • K. Tanaka, H. Yamaki, S. Miwa, and H. Honda, Multi-Level Packet Processing Caches, The 2019 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), 3 pages (Apr 2019).

2018

Conference/workshop proceedings

  • K. Tanaka, H. Yamaki, S. Miwa, and H. Honda, Optimizing Memory Hierarchy within an Internet Router for High-Throughput and Energy-Efficient Packet Processing, ACM Student Research Competition (in conjunction with the 51st Annual ACM/IEEE International Symposium on Microarchitecture) (poster presentation) (Oct 2018).
  • H. Yamaki, H. Nishi, S. Miwa, and H. Honda, Data Prediction for Response Flows in Packet Processing Cache, 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC), No.110 (Jun 2018).
  • I. Miyoshi, S. Miwa, K. Inoue, and M. Kondo, Run-Time DFS/DCT Optimization for Power-Constrained HPC Systems, The International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2018) (poster presentation) (Jan 2018).

Invited conference/seminar talks

  • T. Ono, Y. Kakibuka, N. Jain, A. Bhatele, S. Miwa, and K. Inoue, Extending A Network Simulator for Power/Performance Prediction of Large Scale Interconnection Networks, Modeling and Simulation of HPC Architectures and Applications (the SIAM PP18 mini-symposium) (Mar 2018).

Books

  • M. Kondo, I. Miyoshi, K. Inoue, and S. Miwa, Power Management Framework for Post-Petascale Supercomputers, Book Chapter in Advanced Software Technologies for Post-Peta Scale Computing—The Japanese Post-Peta CREST Research Project— edited by M. Sato, pp.249–269, Springer (Dec 2018).

2017

Domestic non-refereed symposiums

  • The six technical reports were published.

Invited conference/seminar talks

  • The two seminar talks were done.

2016

Journal articles

  • Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, and H. Nakamura, A Runtime Optimization Selection Framework to Realize Energy Efficient Network-on-Chip, IEICE TRANSACTIONS on Information and Systems, Vol.E99-D, No.5, pp.1-10 (2016).

Conference/workshop proceedings

  • M. Ohba, S. Miwa, S. Shindo, T. Tsumura, H. Yamaki, and H. Honda, Initial Study of Reconfigurable Neural Network Accelerators, The 7th International Workshop on Advances in Networking and Computing (poster presentation), pp.707-709, (Nov 2016).
  • S. Shindo, M. Ohba, T. Tsumura, and S. Miwa, Evaluation of Task Mapping on Multicore Neural Network Accelerators, The 4th International Workshop on Computer Systems and Architectures, pp.415-421, (Nov 2016).

Domestic non-refereed symposium

  • The five technical reports were published.

Invited conference talks

  • S. Miwa, Low-power computers with increased hardware, IPSJ-ONE in the 78th National Convention of IPSJ, (Mar 2016).

2015

Conference/workshop proceedings

  • S. Miwa, and H. Nakamura, Profile-based Power Shifting in Interconnection Networks with On/Off Links, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15), pp.37:1-37:11 (Nov 2015).
  • S. Miwa, and H. Honda, Memory Hotplug for Energy Savings of HPC systems, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15, poster) (Nov 2015).
  • E. Arima, H. Noguchi, T. Nakada, S. Miwa, S. Takeda, S. Fujita, and H. Nakamura, Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches, The 33rd IEEE International Conference on Computer Design (ICCD'15), pp.157-164 (Oct 2015).
  • Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, and H. Nakamura, Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections, The 33rd IEEE International Conference on Computer Design (ICCD'15) (poster presentation), pp.484-487 (Oct 2015).
  • E. Arima, S. Miwa, T. Nakada, S. Takeda, H. Noguchi, S. Fujita, and H. Nakamura, Subarray Level Power-Gating in STT-MRAM Caches to Mitigate Energy Impact of Peripheral Circuits, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster presentation), (June 2015).

Invited conference talks

  • S. Takeda, H. Noguchi, K. Nomura, S. Fujita, S. Miwa, E. Arima, T. Nakada, and H. Nakamura, Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors, The 12th International SoC Design Conference, pp.153-154 (Nov 2015).

Domestic seminar

  • Y. Ishikawa, A. Koshiba, R. Sakamoto, Y. Wada, S. Miwa, M. Kondo, M. Namiki, H. Honda: Initial Study for Operand-Aware Power Gating on Execution Units, IPSJ-SIGARC-209 (in Japanese), No.14, pp.1-2, 2015 (to appear).

Book review

  • S. Miwa: Biblio Talk "THINK LIKE ZUCK", IPSJ Magagine (in Japanese), Vol.56, No.5, pp.500-501 (2015).

Before 2014

Miwa lab started since Mar 2015. You can see the past publications by Assoc. Prof. Miwa in his personal web site.